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| Integrated Device Technology, Inc. BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT - 1024 x 9-BIT 1024 x 18-BIT - 2048 x 9-BIT DESCRIPTION: IDT72510 IDT72520 FEATURES: * Two side-by-side FIFO memory arrays for bidirectional data transfers * 512 x 18-Bit - 1024 x 9-Bit (IDT72510) * 1024 x 18-Bit - 2048 x 9-Bit (IDT72520) * 18-bit data bus on Port A side and 9-bit data bus on Port B side * Can be configured for 18-to-9-bit, 36-to-9-bit, or 36-to-18bit communication * Fast 25ns access time * Fully programmable standard microprocessor interface * Built-in bypass path for direct data transfer between two ports * Two fixed flags, Empty and Full, for both the A-to-B and the B-to-A FIFO * Two programmable flags, Almost-Empty and Almost-Full for each FIFO * Programmable flag offset can be set to any depth in the FIFO * Any of the eight internal flags can be assigned to four external flag pins * Flexible reread/rewrite capabilities. * On-chip parity checking and generation * Standard DMA control pins for data exchange with peripherals * IDT72510 and IDT72520 available in the the 52-pin PLCC package The IDT72510 and IDT72520 are highly integrated firstin, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side memory arrays for data transfers in two directions. The BiFIFOs have two ports, A and B, that both have standard microprocessor interfaces. All BiFIFO operations are controlled from the 18-bit wide Port A. The BiFIFOs incorporate bus matching logic to convert the 18-bit wide memory data paths to the 9-bit wide Port B data bus. The BiFIFOs have a bypass path that allows the device connected to Port A to pass messages directly to the Port B device. Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers. The IDT BiFIFOs have programmable flags. Each FIFO memory array has four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to any depth through the Configuration Registers. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through one Configuration Register. Port B has parity, reread/rewrite and DMA functions. Parity generation and checking can be done by the BiFIFO on data passing through Port B. The Reread and Rewrite con- SIMPLIFIED BLOCK DIAGRAM 18-Bit FIFO 18-bits Data Bypass Path 9-bits 9-bits Data Port A 18-Bit FIFO Port B Registers Control Processor Interface A Processor Interface B Control Flags Programmable Flag Logic Handshake Interface DMA The IDT logo is a registered trademark of Integrated Device Techology, Inc. 2669 drw 01 COMMERCIAL TEMPERATURE RANGE (c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. DECEMBER 1995 DSC-2669/- 5.31 1 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE trols will read or write Port B data blocks multiple times. The BiFIFOs have three pins, REQ, ACK and CLK, to control DMA transfers from Port B devices. PIN CONFIGURATION LDREW LDRER GND GND DA16 DSA VCC DA9 DA8 INDEX 7654 DA10 DA11 DA12 DA13 DA14 DA15 DA17 A0 A1 FLGD FLGC FLGB FLGA 8 9 10 11 12 13 14 15 16 17 18 19 20 32 RS 1 52 51 50 49 48 47 46 45 44 43 42 41 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 CSA R/WA J52-1 40 39 38 37 36 35 34 RER REW REQ ACK CLK DB0 21 22 23 24 25 26 27 28 29 30 31 32 33 WB (R/WB) RB (DSB) DB8 DB7 DB6 DB5 DB4 DB3 DB2 GND PLCC TOP VIEW GND 5.31 VCC DB1 2 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTIONS Symbol DA0-DA15 DA16-DA17 Name Data A Parity A I/O I/O I/O Description Data inputs and outputs for 16 bits of the 18-bit Port A bus. DA16 is the parity bit for DA0-DA7. DA17 is the parity bit for DA8DA15. DA16 and DA17 can be used as two extra data bits if the parity generate function is disabled. Port A is accessed when Chip Select A is LOW. Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the falling edge of Data Strobe when Chip Select is LOW. This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH, data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data is written into Port A on the rising edge of DSA. When Chip Select A is asserted, A0, A1, and Read/Write A are used to select one of six internal resources. Data inputs and outputs for 8 bits of the 9-bit Port B bus. DB8 is the parity bit for DB0-DB7. DB8 can be used as a data bit if the parity generate function is disabled. If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface (RB) or as part of a Motorola-style interface (DSB). As an Intel-style interface, data is read from Port B on a falling edge of RB. As a Motorola-style interface, data is read on the falling edge of DSB or written on the rising edge of DSB through Port B. The Default is Intelstyle processor mode (RB as an input). If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface (WB) or as part of a Motorola-style interface (R/WB). As an Intel style interface, data is written to Port B on a rising edge of WB. As a Motorola-style interface, data is read (R/WB = HIGH) or written (R/ WB = LOW) to Port B in conjunction with a Data Strobe B falling or rising edge. The Default is Intel-style processor mode (WB as input). Loads A-to-B FIFO Read Pointer with the value of the Reread Pointer when LOW. Loads B-to-A FIFO Write Pointer with the value of the Rewrite Pointer when LOW. Loads the Reread Pointer with the value of the A-to-B FIFO Read Pointer when HIGH. This signal is accessible through the Command Register. Loads the Rewrite Pointer with the value of the B-to-A FIFO Write Pointer when HIGH. This signal is accessible through the Command Register. When Port B is programmed in peripheral mode, asserting this pin begins a data transfer. Request can be programmed either active HIGH or active LOW. 2669 tbl 01 CSA DSA R/WA Chip Select A Data Strobe A I I Read/Write A I A0, A1 DB0-DB7 DB8 Addresses Data B Parity B Read B I I/O I/O I or O RB (DSB) WB (R/WB) Write B I or O RER REW LDRER Reread Rewrite Load Reread I I I LDREW Load Rewrite I REQ Request I 5.31 3 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTIONS Symbol ACK Name Acknowledge I/O O Description When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed either active HIGH or active LOW. This pin is used to generate timing for ACK, RB, WB, DSB and R/WB when Port B is in the peripheral mode. These four outputs pins can be assigned to any one of the eight internal flags in the BiFIFO. Each of the two internal FIFOs (A-to-B and B-to-A) has four internal flags: Empty, Almost-Empty, AlmostFull, and Full. If parity checking is enabled, the FLGA pin can also be assigned as a parity error output. A LOW on this pin will perform a reset of all BiFIFO functions. Software reset can be achieved through command register. There are two +5V power pins on all four devices. There are four ground pins 2669 tbl 02 CLK FLGA-FLGD Clock Flags I O RS VCC GND Reset Power Ground I 5.31 4 ReRead Pointer Load Reread Write Pointer Read Pointer Port B Control (DB8) MUX Reread LDRER LDREW CSA DSA AB FIFO Parity Bit 17 Parity Bit 16 Data Bits 8-15 1 Parity Generate/ Check R/WA A1 A0 Port A Control RB (DSB) WB (R/WB) RER REW 18 Data Bits 0-7 Bypass Path (DB0-DB7) 8 8 8 Read Parity Error IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO DETAILED BLOCK DIAGRAM Port A MUX DA0-DA17 Port B DB0-DB8 Parity Generate/ Check 9 (DA0-DA7,DA16) BA FIFO Parity Bit 17 Parity Bit 16 9 Odd Byte Register Data Bits 8-15 18 Data Bits 0-7 8 5.31 Reset RS DMA Control REQ* ACK* CLK Read Pointer Load Rewrite Command Status Configuration 0 Configuration 1 Configuration 2 Configuration 3 Configuration 4 Configuration 5 Configuration 6 Configuration 7 ReWrite Pointer Rewrite Write Pointer Write Parity Error 16 (DA0-DA15) FLGA* FLGB* FLGC* FLGD* Programmable Flag Logic COMMERCIAL TEMPERATURE RANGE 2669 drw 03 5 NOTES: (*) Can be programmed either active high or active low in internal configuration registers. () Accessible through internal registers. () Can be programmed through an internal configuration register to be either an input or an output. 2669 drw 04 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE FUNCTIONAL DESCRIPTION IDT's BiFIFO family is versatile for both multiprocessor and peripheral applications. Data can be sent through both FIFO memories concurrently, thus freeing both processors from laborious direct memory access (DMA) protocols and frequent interrupts. Two full 18-bit wide FIFOs are integrated into the IDT BiFIFO, making simultaneous data exchange possible. Each FIFO is monitored by separate internal read and write pointers, so communication is not only bidirectional, it is also totally independent in each direction. The processor connected to Port A of the BiFIFO can send or receive messages directly to the Port B device using the BiFIFO's 9-bit bypass path. The BiFIFOs can be used in three different bus configurations: 18 bits to 9 bits, 36 bits to 9 bits and 36 bits to 18 bits. One BiFIFO can be used for the 18- to 9-bit configuration, and two BiFIFOs are required for 36- to 9-bit or 36- to 18-bit configurations. Bits 11 and 12 of Configuration Register 5 determine the BiFIFO configuration (see Table 11 for Configuration Register 5 format). The microprocessor or microcontroller connected to Port A controls all operations of the BiFIFOs. Thus, all Port A interface pins are inputs driven by the controlling processor. Port B can be programmed to interface either with a second processor or a peripheral device. When Port B is programmed in processor interface mode, the Port B interface pins are inputs driven by the second processor. If a peripheral device is connected to the BiFIFOs, Port B is programmed to peripheral interface mode and the interface pins are outputs. 18- to 9-bit Configurations A single BiFIFO can be configured to connect an 18-bit processor to another 9-bit processor or a 9-bit peripheral. Bits 11 and 12 of Configuration Register 5 should be set to 00 for a stand-alone configuration. Figures 1 and 2 show the BiFIFO in 18- to 9-bit configurations for processor and peripheral interface modes respectively. 36- to 9-bit Configurations Two BiFIFOs can be hooked together to create a 36-bit to 9-bit configuration. This means that a 36-bit processor can 36-BIT PROCESSOR to 18-BIT PROCESSOR CONFIGURATION IDT BiFIFO (Stand-Alone) Cntl A Cntl B ACK REQ CLK Data A Data B Control Logic Address Control Control Logic Processor A Processor B Control 36-bit bus Data 36 18-bit bus IDT BiFIFO (Stand-Alone) Cntl A Cntl B ACK REQ CLK Data A Data B 18 9 Data 18 RAM RAM 2669 drw 04 Figure 1. 36- to 18-Bit Processor Interface Configuration NOTE: 1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that Cntl A refers to CSA, A1, A0, R/WA and DSA; Cntl B refers to R/WB and DSB or RB and WB. 5.31 6 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE 36-BIT PROCESSOR to 18-BIT PERIPHERAL CONFIGURATION IDT BiFIFO (Stand-Alone) Cntl A Cntl B ACK REQ CLK Data A Data B DMA or System Clock Processor Address Control Control Logic Peripheral Controller Cntl ACK REQ 18-bit bus Data 36 36-bit bus Data 18 I/O Data IDT BiFIFO (Stand-Alone) Cntl A Cntl B ACK REQ CLK Data A Data B 18 9 RAM 2669 drw 05 Figure 2. 36- to 18-Bit Peripheral Interface Configuration NOTE: 1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that Cntl A refers to CSA, A1, A0, R/WA and DSA; Cntl B refers to R/WB and and WB. DSB or RB talk to a 9-bit processor or a 9-bit peripheral. Both BiFIFOs are programmed simultaneously through Port A by placing one command word on the most significant 16 data bits and one command word on the least significant 16 data bits (parity bits should be ignored). One BiFIFO must be programmed as the master device and the other BiFIFO is the slave device. Bits 11 and 12 of Configuration Register 5 are set to 10 for the slave device and 11 for the master device. The first two 9-bit words on Port B are read from or written to the slave device and the next two 9-bit words go to the master device. When both BiFIFOs are in peripheral interface mode, the Port B interface pins of the master device are outputs and this BiFIFO controls the bus. The Port B interface pins of the slave device are inputs driven by the master BiFIFO. Two BiFIFOs are connected in Figure 4 to create a 36- to 9-bit peripheral interface. The two BiFIFOs shown in Figure 3 are configured to connect a 36-bit processor to a 9-bit processor. 36- to 18-bit Configurations In a 36- to 18-bit configuration, two BiFIFOs operate in parallel. Both BiFIFOs are programmed simultaneously, 16 data bits to each device with the 4 parity bits ignored. Both BiFIFOs must be programmed into stand-alone mode for a 36-bit processor to communicate with an 18-bit processor or an 18-bit peripheral. This means that bits 11 and 12 of Configuration Register 5 must be set to 00. This configuration can be extended to wider bus widths (54- to 27-bits, 72- to 36-bits, ...) by adding more BiFIFOs to the configuration. Figures 1 and 2 show multiple BiFIFOs configured for processor and peripheral interface modes respectively. Processor Interface Mode When a microprocessor or microcontroller is connected to Port B, all BiFIFOs in the configuration must be programmed to processor interface mode. In this mode, all Port B interface controls are inputs. Both REQ and CLK pins should be pulled LOW to ensure that the set-up and hold time requirements for these pins are met during reset. Figures 1 and 3 show BiFIFOs in processor interface mode. Peripheral Interface Mode If Port B is connected to a peripheral controller, all BiFIFOs in the configuration must be programmed in the peripheral interface mode. To assure fixed high states for RB and WB before they are programmed into an output, both pins should be pulled-up to VCC with 10K resistors. If the BiFIFOs are in stand-alone configuration mode (18- to 9-bit, 36- to 18-bit, ...), then the Port B interface pins are all outputs. Of course, only one set of Port B interface pins should be used to control a single peripheral device, while the other interface pins are all ignored. Figure 2 shows stand7 5.31 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE alone configuration BiFIFOs connected to a peripheral. In a 36- to 9-bit configuration, the master device controls the bus. The Port B interface pins of the master device are outputs and the interface pins of the slave device are inputs. A 36- to 9-bit configuration of two BiFIFOs connected to a peripheral is shown in Figure 4. Port A Interface The BiFIFO is straightforward to use in microprocessorbased systems because each BiFIFO port has a standard microprocessor control set. Port A has access to six re- sources: the AB FIFO, the BA FIFO, the 9-bit direct data bus (bypass path), the configuration registers, status and command registers. The Port A Address and Read/Write pins determine the resource being accessed as shown in Table 1. Data Strobe is used to move data in and out of the BiFIFO. When either of the internal FIFOs are accessed 18 bits of data are transferred across Port A. Since the bypass path is only 9 bits wide, the least significant byte with parity (DA0-DA7, DA16) is used on Port A. All of the registers are 16 bits wide which means only the data bits (DA0-DA15) are passed by Port A. 36-BIT PROCESSOR to 9-BIT PROCESSOR CONFIGURATION IDT BiFIFO (Master) Cntl A Cntl B ACK REQ CLK Data A Data B Control Logic Address Control Control Logic Processor A Processor B Control Data 36-bit bus 9-bit bus Data IDT BiFIFO (Slave) Cntl A Cntl B ACK REQ CLK Data A Data B 18 RAM RAM 2669 drw 06 Figure 3. 36- to 9-Bit Processor Interface Configuration NOTE: 1. Cntl A refers to CSA, A1, A0, R/WA and DSA; Cntl B refers to R/WB and DSB or RB and WB. 5.31 8 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE 36-BIT PROCESSOR to 9-BIT PERIPHERAL CONFIGURATION IDT BiFIFO (Master) Cntl A Cntl B ACK REQ CLK Data A Data B DMA or System Clock Processor Address Control Control Logic Peripheral Controller Cntl ACK REQ 9-bit bus Data 36-bit bus Data I/O Data IDT BiFIFO (Slave) Cntl A Cntl B ACK REQ CLK Data A Data B 18 RAM 2669 drw 07 Figure 4. 36- to 9-Bit Peripheral Interface Configuration NOTE: 1. Cntl A refers to CSA, A1, A0, R/WA and DSA; Cntl B refers to R/WB and DSB or RB and WB. 5.31 9 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE PORT A RESOURCES COMMAND OPERATIONS Write AB FIFO 9-bit Bypass Path Configuration Registers Command Register Disabled 2669 tbl 03 CS CSA 0 0 0 0 1 A1 0 0 1 1 X A0 0 1 0 1 X Read BA FIFO 9-bit Bypass Path Configuration Registers Status Register Disabled Command Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Function Reset BiFIFO (see Table 3) Select Configuration Register (see Table 4) Load Reread Pointer with Read Pointer Value Load Rewrite Pointer with Write Pointer Value Load Read Pointer with Reread Pointer Value Load Write Pointer with Rewrite Pointer Value Set DMA Transfer Direction (see Table 5) Set Status Register Format (see Table 6) Increment in byte for AB FIFO Read Pointer (Port B) Increment in byte for BA FIFO Write Pointer (Port B) Clear Write Parity Error Flag Clear Read Parity Error Flag 2669 tbl 04 Table 1. Accessing Port A Resources Using CS A0, and A1 CSA, Bypass Path The bypass path acts as a bidirectional bus transceiver directly between Port A and Port B. The direct connection requires that the Port A interface pins are inputs and the Port B interface pins are outputs. The bypass path is 9 bits wide in an 18- to 9-bit configuration or in a 36- to 9-bit configuration. Only in the 36- to 18-bit configuration is the bypass path 18 bits wide. During bypass operations, the BiFIFOs must be programmed into peripheral interface mode. Bit 10 of Configuration Register 5 (see Table 11) is set to 1 for peripheral interface mode. In a 36- to 9-bit configuration, both Port B data buses will be active. Data written into Port A will appear on both master and slave Port B buses concurrently. To avoid Port B bus contention, the data on DA0-DA7 and DA16 of both BiFIFOs should be exactly the same. Data read from Port A will appear on pins DA0-DA7 and DA16 of both BiFIFOs within the same 36bit word. Command Register Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers. The Command Register is written by setting CSA = 0, A1 = 1, A0 = 1. Commands written into the BiFIFO have a 4-bit opcode (bit 8 - bit 11) and a 3-bit operand (bit 0 - bit 2) as shown in Figure 5. The commands can be used to reset the BiFIFO, to select the Configuration Register, to perform intelligent reread/rewrite, to set the Port B DMA direction, to set the Status Register format, to modify the Port B Read and Write Pointers, and to clear Port B parity errors. The command opcodes are shown in Table 2. The reset command initializes different portions of the BiFIFO depending on the command operand. Table 3 shows the reset command operands. The Configuration Register address is set directly by the command operands shown in Table 4. Intelligent reread/rewrite is performed by changing the Port B Read Pointer with the Reread Pointer or by changing the Table 2. Functions Performed by Port A Commands Port B Write Pointer with the Rewrite Pointer. No command operands are required to perform a reread/rewrite operation. When Port B of the BiFIFO is in peripheral mode, the DMA direction is controlled by the Command Register. Table 5 shows the Port B read/write DMA direction operands. The BiFIFO supports two Status Register formats. Status Register format 1 gives all the internal flag status, while Status Register format 0 provides the data in the Odd Byte Register. Table 6 gives the operands for selecting the appropriate Status Register format. See Table 8 for the details of the two Status Register formats. Two commands are provided to increment the Port B Read and Write Pointers in case reread/rewrite is performed. Incrementing the pointers guarantees that pointers will be on a word boundary when an odd number of bytes is transmitted through Port B. No operands are required for these commands. When parity check errors occur on Port B, a clear parity error command is needed to remove the parity error. There are no operands for these commands. Reset The IDT72510 and IDT72520 have a hardware reset pin (RS) that resets all BiFIFO functions. A hardware reset requires the following four conditions: RB and WB must be HIGH, RER and REW must be HIGH, LDRER and LDREW must be LOW, and DSA must be HIGH (Figure 9). After a hardware reset, the BiFIFO is in the following state: Configuration Registers 0-3 are 0000H, Configuration Register 4 is set to COMMAND FORMAT 15 12 11 8 7 3 2 0 2669 tbl 05 X X X X Command Opcode X X X X X Command Operand Figure 5. Format for Commands Written into Port A 5.31 10 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE RESET COMMAND FUNCTIONS Reset Operands 000 001 010 011 100 101 110 111 No Operation Reset BA FIFO (Read, Write, and Rewrite Pointers = 0) Reset AB FIFO (Read, Write, and Reread Pointers = 0) Reset BA and AB FIFO Reset Internal DMA Request Circuitry No Operation No Operation Reset All 2669 tbl 06 Function SELECT CONFIGURATION REGISTER COMMAND FUNCTIONS Operands 000 001 010 011 100 101 110 111 Function Select Configuration Register 0 Select Configuration Register 1 Select Configuration Register 2 Select Configuration Register 3 Select Configuration Register 4 Select Configuration Register 5 Select Configuration Register 6 Select Configuration Register 7 2669 tbl 07 Table 4. Select Configuration Register Command Functions. Table 3. Reset Command Functions DMA DIRECTION COMMAND FUNCTIONS 6420H, and Configuration Registers 5 and 7 are 0000H. Additionally, Status Register format 0 is selected, all the pointers including the Reread and Rewrite Pointers are set to 0, the odd byte register valid bit is cleared, the DMA direction is set to BA write, the internal DMA request circuitry is cleared (set to its initial state), and all parity errors are cleared. A software reset command can reset AB pointers and the BA pointers to 0 independently or together. The request (REQ) DMA circuitry can also be reset independently. A software Reset All command resets all the pointers, the DMA request circuitry, and sets all the Configuration Registers to their default condition. Note that a hardware reset is NOT the same as a software Reset All command. Table 7 shows the BiFIFO state after the different hardware and software resets. Operands XX0 XX1 Write BA FIFO Read AB FIFO 2669 tbl 08 Function Table 5. Set DMA Direction Command Functions. Command Only Operates in Peripheral Interface Mode STATUS REGISTER FORMAT COMMAND FUNCTIONS Operands XX0 XX1 Function Status Register Format 0 Status Register Format 1 2669 tbl 09 Table 6. Command Functions to Set the Status Register Format STATE AFTER RESET Hardware Reset (RS asserted) B A (001) AB (010) Software Reset BA and AB (011) -- -- -- -- -- 0 0 clear -- -- -- Internal Request (100) -- -- -- -- -- -- -- -- -- clear -- All (111) Configuration Registers 0-3 Configuration Register 4 Configuration Register 5 Configuration Register 7 Status Register format BA Read, Write, Rewrite Pointers AB Read, Write, Reread Pointers Odd byte register valid bit DMA direction DMA internal request Parity errors 0000H 6420H 0000H 0000H 0 0 0 clear B A write clear clear -- -- -- -- -- 0 -- clear -- -- -- -- -- -- -- -- -- 0 -- -- -- -- 0000H 6420H 0000H 0000H -- 0 0 clear -- clear -- 2669 tbl 10 Table 7. The BiFIFO State After a Reset Command 5.31 11 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE Status Register The Status Register reports the state of the programmable flags, the DMA read/write direction, the Odd Byte Register valid bit, and parity errors. The Status Register is read by setting CSA = 0, A1 = 1, A0 = 1 (see Table 1). There are two Status Register formats that are set by a Status Register format command. Format 0 stores the Odd Byte Register data in the lower eight bits of the Status Register, while format 1 reports the flag states and the DMA read/write direction in the lower eight bits. The upper eight bits are identical for both formats. The flag states, the parity errors, the Odd Byte Register valid bit, and the Status Register format are all in the upper eight bits of the Status Register. See Table 8 for both Status Register formats. Configuration Registers The eight Configuration Register formats are shown in Table 9. Configuration Registers 0-3 contain the programmable flag offsets for the Almost Empty and Almost Full flags. These offsets are set to 0 when a hardware reset or a software reset all is applied. Note that Table 9 shows that Configuration Registers 0-3 are 10 bits wide to accommodate the 1024 locations in each FIFO memory of the IDT72520. Only 9 least significant bits are used for the 512 locations of the IDT72510; the most significant bit, bit 9, must be set to 0. Configuration Register 4 is used to assign the internal flags to the external flag pins (FLGA-FLGD). Each external flag pin is assigned an internal flag based on the four bit codes shown in Table 10. The default condition for Configuration Register 4 is 6420H as shown in Table 7. The default flag assignments are: FLGD is assigned BA Full, FLGC is assigned BA Empty, FLGB is assigned AB Full, FLGA is assigned AB Empty. Configuration Register 5 is a general control register. The format of Configuration Register 5 is shown in Table 11. Bit 0 sets the Intel-style interface (RB, WB) or Motorola-style interface (DSB, R/WB) for Port B. Bit 1 changes the byte order for data coming through Port B. Bits 2 and 3 redefine Full and Empty Flags for reread/rewrite data protection. Bits 4-9 control the DMA interface and are only applicable in peripheral interface mode. In processor interface mode, these bits are don't care states. Bits 4 and 5 set the polarity of the DMA control pins REQ and ACK, respectively. An internal clock controls all DMA operations. This internal clock is derived from the external clock (CLK). Bit 9 determines the internal clock frequency: the internal clock = CLK or the internal clock = CLK divided by 2. Bit 8 sets whether RB, WB, and DSB are asserted for either one or two internal clocks. Bits 6 and 7 set the number of internal clocks between REQ assertion and ACK assertion. The timing can be from 2 to 5 cycles as shown in Figure 17. Bit 10 controls Port B processor or peripheral interface mode. In processor mode, the Port B control pins (RB, WB, DSB, R/WB) are inputs and the DMA controls are ignored. In peripheral mode, the Port B control pins are outputs and the DMA controls are active. Bits 11 and 12 set the width expansion mode. For 18- to 9-bit configurations or 36- to 18-bit configurations, the BiFIFO should be set in stand-alone mode. For a 36- to 9-bit configuration, one BiFIFO must be in slave mode and the other BiFIFO must be in master mode. The master BiFIFO allows the first two bytes transferred across Port B to go to the slave BiFIFO, then the next two bytes go to the master BiFIFO. Configuration Register 7 controls the parity functions of Port B as shown in Table 12. Either parity generation or parity STATUS REGISTER FORMAT 0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Valid Bit Odd Byte Register Signal STATUS REGISTER FORMAT 1 Bit 0 1 2 3 4 5 6 7 8 Reserved Reserved Reserved DMA Direction AB Empty Flag AB Almost-Empty Flag BA Full Flag BA Almost-Full Flag Valid Bit Write Parity Error Read Parity Error Status Register Format = 1 AB Full Flag AB Almost-Full Flag BA Empty Flag BA Almost-Empty Flag 2669 tbl 12 Signal Write Parity Error Read Parity Error Status Register Format = 0 AB Full Flag AB Almost-Full Flag BA Empty Flag BA Almost-Empty Flag 2669 tbl 11 9 10 11 12 13 14 15 Table 8. The Two Status Register Formats 5.31 12 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE CONFIGURATION REGISTER FORMATS 15 10 9 0 Config. Reg. 0 X 15 X X X X X 10 9 AB FIFO Almost-Empty Flag Offset 0 Config. Reg. 1 X 15 X X X X X 10 9 AB FIFO Almost-Full Flag Offset 0 Config. Reg. 2 X 15 X X X X X 10 9 BA FIFO Almost-Empty Flag Offset 0 Config. Reg. 3 X 15 X X X 12 X 11 X 8 BA FIFO Almost-Full Flag Offset 7 4 3 0 Config. Reg. 4 Flag D Pin Assignment 15 Flag C Pin Assignment Flag B Pin Assignment Flag A Pin Assignment 0 Config. Reg. 5 15 General Control 0 Config. Reg. 6 15 Reserved 0 Config. Reg. 7 NOTE: 1. Bit 9 of Configuration Registers 0-3 must be set to 0 on the IDT72510. Parity Control 2669 tbl 13 Table 9. The BiFIFO Configuration Register Formats checking is enabled for data read and written through Port B. Bit 8 controls parity checking and generation for BA write data. Bit 9 controls parity checking and generation for AB read data. Bit 10 controls whether the parity is odd or even. Bit 11 is used to assign the internal parity checking error to the FLGA pin. When the parity error is assigned to FLGA, the Configuration Register 4 flag assignment for FLGA is ignored. Programmable Flags The IDT BiFIFO has eight internal flags; four of these flags have programmable offsets, the other four are empty or full. Associated with each FIFO memory array are four internal flags, Empty, Almost-Empty, Almost-Full and Full, for the total of eight internal flags. The Almost-Empty and Almost-Full offsets can be set to any depth through the Configuration Registers 0-3 (see Table 9). The offset (or depth) of FIFO RAM array is based on the unit of an 18-bit word. The flags are asserted at the depths shown in Table 13. After a hardware reset or a software reset all, the almost flag offsets are set to 0. Even though the offsets are equivalent, the Empty and Almost-Empty flags have different timing which means that the flags are not coincident. Similarly, the Full and Almost-Full flags are not coincident because of timing. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through Configuration Register 4 (see Table 10). For the specific flag timings, see Figures 20-23. The current state of all eight flags is available in the Status Register in Status Register format 1. In Status Register format 0, only four flags can be found in the Status Register (see Table 8). EXTERNAL FLAG ASSIGNMENT CODES Assignment Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Internal Flag Assigned to Flag Pin AB Empty AB Almost-Empty AB Full AB Almost-Full BA Empty BA Almost-Empty BA Full BA Almost-Full AB Empty AB Almost-Empty AB Full AB Almost-Full BA Empty BA Almost-Empty BA Full BA Almost-Full 2669 tbl 14 Table 10. Configuration Register 4 Internal Flag Assignments to External Flag Pins. 5.31 13 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE Port B Interface Port B also has parity, reread/rewrite and DMA functions. Port B can be configured to interface to either Intel-style (RB, WB) or Motorola-style (DSB, R/WB) devices in Configuration Register 5 (see Table 11). Port B can also be configured to talk to a processor or a peripheral device through Configuration Register 5. In processor interface mode, the Port B interface controls are inputs. In peripheral interface mode, the Port B interface controls are outputs. After a hardware reset or a software Reset All command, Port B defaults to an Intel-style processor interface; the controls are inputs. Two 9-bit words are put together to create each 18-bit word stored in the internal FIFOs. The first 9-bit word written to Port B goes into the Odd Byte Register shown in the detailed block diagram. The Odd Byte Register valid bit (Bit 8) in the Status Register is 1 when this first 9-bit word is written. The data bits from Port B (DB0-DB7) are also stored in the lower 8 bits of the Status Register when Status Register format 0 is selected (see Table 8). The second write on Port B moves the 9-bits from Port B and the 9-bits in the Odd Byte Register into the BA FIFO and advances the BA Write Pointer. The Status Register valid bit is set to 0 after the second write. When Port B reads data from the AB FIFO, two buffers choose which 9 of the 18 memory bits are sent to Port B. These buffers alternate between the upper 9 bits (DA8-DA15, DA17) and the lower 9 bits (DA0-DA7, DA16). The AB Read Pointer is advanced after every two Port B reads. The BiFIFO can be set to order the 9-bit data so the first 9- CONFIGURATION REGISTER 5 FORMAT Bit 0 1 Function Select Port B Interface 0 1 0 1 2 3 4 5 Full Flag Definition Empty Flag Definition REQ Pin Polarity ACK Pin Polarity 0 1 0 1 0 1 0 1 00 7-6 REQ / ACK Timing 01 10 11 8 9 10 Port B Read and Write Timing Control for Peripheral Mode Internal Clock Frequency Control Port B Interface Mode Control 0 1 0 1 0 1 00 12-11 Width Expansion Mode Control 13 14 15 Unused Unused Unused 2669 tbl 15 RB & WB or DSB & R/WB Byte Order of 18-bit Word Pins are DSB and R/WB (Motorola-style interface) Lower byte DA7-DA0 and parity DA16 are read or written first on Port B Upper byte DA15-DA8 and parity DA17 are read or written first on Port B Full Flag is asserted when write pointer meets read pointer Full Flag is asserted when write pointer meets reread pointer Empty Flag is asserted when read pointer meets write pointer Empty Flag is asserted when read pointer meets rewrite pointer REQ pin active HIGH REQ pin active LOW ACK pin active LOW ACK pin active HIGH 2 internal clocks between REQ assertion and ACK assertion 3 internal clocks between REQ assertion and ACK assertion 4 internal clocks between REQ assertion and ACK assertion 5 internal clocks between REQ assertion and ACK assertion Pins are RB and WB (Intel-style interface) RB, WB, and DSB are asserted for 1 internal clock RB, WB, and DSB are asserted for 2 internal clocks internal clock = CLK internal clock = CLK divided by 2 Processor interface mode (Port B controls are inputs) Peripheral interface mode (Port B controls are outputs) Stand-alone mode (18- to 9-bits, 36- to 18-bits) Reserved Slave width expansion mode (36- to 9-bits) Master width expansion mode (36- to 9-bits) 01 10 11 Table 11. BiFIFO Configuration Register 5 Format 5.31 14 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE CONFIGURATION REGISTER 7 FORMAT BIT 0-7 8 9 10 11 12-15 FUNCTION Unused Parity Input Control BA Parity Output Control AB Parity Odd/Even Control Assign Parity Error to Flag A Pin Unused Table 12. BiFIFO Configuration Register 7 Format 0 1 0 1 0 1 0 1 Disable Parity Generate, Enable Parity Check Enable Parity Generate, Disable Parity Check Disable Parity Generate, Enable Parity Check Enable Parity Generate, Disable Parity Check Odd Even No Parity Error Output Parity Error on Flag A Pin 2669 tbl 16 bits go to the LSB (DA0-DA7, DA16) or the MSB (DA8-DA15, DA17) of Port A. This data ordering is controlled by bit 1 of Configuration Register 5 (see Table 11). DMA Control Interface The BiFIFO has DMA control to simplify data transfers with peripherals. For the BiFIFO DMA controls (REQ, ACK and CLK) to operate, the BiFIFO must be in peripheral interface mode (Configuration Register 5, Table 11). DMA timing is controlled by the external clock input, CLK. An internal clock is derived from this CLK signal to generate the RB, WB, DSB and R/WB output signals. The internal clock also determines the timing between REQ assertion and ACK assertion. Bit 9 of Configuration Register 5 determines whether the internal clock is the same as CLK or whether the internal clock is CLK divided by 2. Bit 8 of Configuration Register 5 sets whether RB, WB and DSB are asserted for 1 or 2 internal clocks. Bits 6 and 7 of Configuration Register 5 set the number of clocks between REQ assertion and ACK assertion. The clocks between REQ assertion and ACK assertion can be 2, 3, 4 or 5. Bits 4 and 5 of Configuration Register 5 set the polarity of the REQ and ACK pins, respectively. A DMA transfer command sets the Port B read/write direction (see Table 5). The timing diagram for DMA transfers is shown in Figure 17. The basic DMA transfer starts with REQ assertion. After 2 to 5 internal clocks, ACK is asserted by the BiFIFO. ACK will not be asserted if a read is attempted on an Empty AB FIFO or if a write is attempted on a Full BA FIFO. If the BiFIFO is in Motorola-style interface mode, R/WB is set at the same time that ACK is asserted. One internal clock later, DSB is asserted. If the BiFIFO is in Intel-style interface mode, either RB or WB is asserted one internal clock after ACK assertion. These read/write controls stay asserted for 1 or 2 internal clocks, then ACK, DSB, RB and WB are made inactive. This completes the transfer of one 9-bit word. On the next rising edge of CLK, REQ is sampled. If REQ is still asserted, another DMA transfer starts with the assertion of ACK. Data transfers will continue as long as REQ is asserted. Parity Checking and Generation Parity generation or checking is performed by the BiFIFO on data passing through Port B. Parity can either be odd or even as determined by Bit 10 of Configuration Register 7. When parity checking is enabled, DB8 is treated as a data bit. DB8 data will be passed to DA16 (bypass operation) or stored in the RAM array (FIFO operation) for B->A operation; similarly, DA16 or parity bits from the RAM array will be passed to DB8 for A->B operations. A->B read parity errors and B->A write parity errors are shown in Bit 9 and 10 in the Status Register. If an external parity error signal is required, a logical OR of the INTERNAL FLAG TRUTH TABLE Number of Words in FIFO From 0 1 n+1 D-m D To 0 n D - (m + 1) D-1 D Empty Flag Asserted Not Asserted Not Asserted Not Asserted Not Asserted Almost-Empty Flag Asserted Asserted Not Asserted Not Asserted Not Asserted Almost-Full Flag Not Asserted Not Asserted Not Asserted Asserted Asserted Full Flag Not Asserted Not Asserted Not Asserted Not Asserted Asserted 2669 tbl 17 NOTE: 1. BiFIFO flags can be assigned to external flag pins to be observed. D = FIFO depth (IDT72510 = 512, IDT72520 = 1024), n = Almost-Empty flag offset, m = Almost-Full flag offset. Table 13. Internal Flag Truth Table. 5.31 15 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE two parity error bits is brought out to FLGA pin by setting Bit 11 of Configuration Register 7. Parity generation creates the ninth bit. This ninth bit is placed on DB8 for A->B read operation, and on DA16 or RAM array for B->A write operation. It is recommended that if the parity pins (DB8, DA16, and DA17) are not used, they should be pulled down with 10K resistors for noise immunity. Intelligent Reread/Rewrite Intelligent reread/rewrite is a method the BiFIFO uses to help assure data integrity. Port B of the BiFIFO has two extra pointers, the Reread Pointer and the Rewrite Pointer. The Reread Pointer is associated with the A->B FIFO Read Pointer, while the Rewrite Pointer is associated with the B->A FIFO Write Pointer. The Reread Pointer holds the start address of a data block in the A->B FIFO RAM, and the Read Pointer is the current address of the same FIFO RAM array. By loading the Read Pointer with the value held in the Reread Pointer (RER asserted), reads will start over at the beginning of the data block. In order to mark the beginning of a data block, the Reread Pointer should be loaded with the Read Pointer value (LDRER asserted) before the first read is performed on this data block. Figure 6 shows a Reread operation. Similarly, the Rewrite Pointer holds the start address of a data block in the B->A FIFO RAM, while the Write Pointer is the current address within the RAM array. The operation of the REW and LDREW is identical to the RER and LDRER discussed above. Figure 7 shows a Rewrite operation. For the reread data protection, Bit 2 of Configuration Register 5 can be set to 1 to prevent the data block form being overwritten. In this way, the assertion of A->B full flag will occur when the write pointer meets the reread pointer instead of the read pointer as in the normal definition. For the rewrite data protection, Bit 3 of Configuration Register 5 can be set to 1 to prevent the data block from being read. In this case, the assertion of B->A empty flag will occur when the read pointer meets the rewrite pointer instead of the write pointer. In conclusion, Bit 2 and 3 of Configuration Register 5 are used to redefine Full & Empty flags for data block partition. Although it can serve the purpose of data protection, the setting of these 2 bits is independent of the functions caused by RER/REW, or LDRER/LDREW assertions. REREAD OPERATIONS (1,2) Reread Pointer Reread function REWRITE OPERATIONS (3,4) Read Pointer Write Pointer AB FIFO Load Reread function Write Pointer BA FIFO Load Rewrite function Rewrite Pointer Read Pointer 2669 drw 08 Rewrite function NOTES: 1. If bit 3 is set to 1, Empty flag asserted if Read = Rewrite Full flag asserted if Read + FIFO size = Write 2. If bit 3 is set to 0, Empty flag asserted if Read = Write Full flag asserted if Read + FIFO size = Write Figure 7. BiFIFO Rewrite Operations NOTES: 1. If bit 2 is set to 1, Empty flag asserted if Read = Write Full flag asserted if Reread + FIFO size = Write 2. If bit 2 is set to 0, Empty flag asserted if Read = Write Full flag asserted if Read + FIFO size = Write Figure 6. BiFIFO Reread Operations 2669 drw 09 5.31 16 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM Rating Terminal Voltage with Respect to Ground Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 Unit V RECOMMENDED DC OPERATING CONDITIONS Symbol VCC GND Parameter Supply Voltage Supply Voltage Input HIGH Voltage Input LOW Voltage Min. 4.5 0 2.0 -- Typ. 5.0 0 -- -- Max. 5.5 0 -- 0.8 Unit V V V V 2669 tbl 19 TA TBIAS TSTG IOUT 0 to +70 -55 to +125 -55 to +125 50 C C C mA VIH VIL(1) NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. NOTE: 2669 tbl 18 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. DC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5V 10%, TA = 0C to +70C) IDT72510L IDT72520L Commercial tA = 25, 35, 50 ns Symbol I IL (1) Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage I OUT = -1mA Output Logic "0" Voltage IOUT = 4mA Average VCC Power Supply Current Average Standby Current (RB = WB = DSA = VIH) Min. -1 -10 2.4 -- -- -- Typ. -- -- -- -- 150 16 Max. 1 10 -- 0.4 220 30 Unit A A V V mA mA 2669 tbl 20 IOL(2) VOH VOL ICC1(3) ICC2(3) NOTES: 1. Measurements with 0.4V VIN VCC, DSA = DSB VIH. 2. Measurements with 0.4V VOUT VCC, DSA = DSB VIH. 3. Measurements are made with outputs open. Tested at f = 20 MHz. +5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 8 2669 tbl 21 1.1 k D.U.T. 680 30 pF * CAPACITANCE (TA = +25C, f = 1.0MHz) Symbol CIN (2) COUT (1,2) Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 12 Unit pF pF 2669 tbl 22 2669 drw 10 NOTES: 1. With output deselected. 2. Characterized values, not currently tested. or equivalent circuit Figure 8. Output Load * Includes jig and scope capacitances 5.31 17 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V10%, T = 0C to +70C) A Commercial IDT72510L25 IDT72520L25 Symbol tRSC tRS tRSS tRSR tRSF Parameter Reset cycle time Reset pulse width Reset set-up time Reset recovery time Flag reset pulse width Min. 35 25 25 10 -- Max. -- -- -- -- 35 RESET TIMING (Port A and Port B) 45 35 35 10 -- -- -- -- -- 45 65 50 50 15 -- -- -- -- -- 65 ns ns ns ns ns 9 9 9 9 9 IDT72510L35 IDT72520L35 Min. Max. IDT72510L50 IDT72520L50 Min. Max. Unit Timing Figure PORT A TIMING taA taLZ Port A access time Read or write pulse LOW to data bus at Low-Z Read or write pulse HIGH to data bus at High-Z Data valid from read pulse HIGH Read cycle time Read pulse width Read recovery time up time taH taDS taDH (1) taWC taWPW taWR taWRCOM time -- 5 25 -- -- 5 35 -- -- 5 50 -- ns ns 12, 14, 15 12, 15, 16 taHZ -- 15 -- 20 -- 30 ns 12, 14, 15, 16 taDV taRC taRPW taRR taS 5 35 25 10 5 5 15 0 35 25 10 25 -- -- -- -- -- -- -- -- -- -- -- -- 5 45 35 10 5 5 18 0 45 35 10 35 -- -- -- -- -- -- -- -- -- -- -- -- 5 65 50 15 5 5 30 5 65 50 15 50 -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns 12, 14, 16 12 12, 14, 15 12 10, 12, 16 10, 12 11, 12, 14, 15 11, 12, 14, 15 12 11, 12, 14 12 11 CSA, A0, A1, R/WA set- CSA, A0, A1, R/WA hold Data set-up time Data hold time Write cycle time Write pulse width Write recovery time Write recovery time after a command NOTE: 1. The minimum data hold time is 5ns (10ns for the 80ns speed grade) when writing to the Command or Configuration registers. 2669 tbl 23 5.31 18 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V10%, TA = 0C to +70C) Commercial IDT72510L25 IDT72520L25 Symbol tbA1 tbA2 tbLZ Parameter Port B access time with no parity Port B access time with parity Read or write pulse LOW to data bus at Low-Z Read or write pulse HIGH to data bus at High-Z Data valid from read pulse HIGH Read cycle time Read pulse width Read recovery time R/WB set-up time R/WB hold time Data set-up time with no parity Data hold time with no parity Data set-up time with parity Data hold time with parity Write cycle time Write pulse width Write recovery time Port B access time with no parity Port B access time with parity Clock cycle time Clock pulse HIGH time Clock pulse LOW time Request set-up time Request hold time Delay from a rising clock edge to ACK switching Min. -- -- 5 Max. 25 30 -- PORT B PROCESSOR INTERFACE TIMING -- -- 5 35 42 -- -- -- 5 50 60 -- ns ns ns 13, 14, 15 13, 14, 15 13, 14, 15 IDT72510L35 IDT72520L35 Min. Max. IDT72510L50 IDT72520L50 Min. Max. Unit Timing Figure tbHZ -- 15 -- 20 -- 30 ns 13, 14, 15 tbDV tbRC tbRPW tbRR tbS tbH tbDS1 tbDH1 tbDS2 tbDH2 tbWC tbWPW tbWR tbA1 tbA2 tbCKC tbCKH tbCKL tbREQS tbREQH tbACKL 5 35 25 10 5 5 15 0 18 0 35 25 10 -- -- 15 6 6 5 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25 30 -- -- -- -- -- 15 5 45 35 10 5 5 18 0 22 0 45 35 10 -- -- 20 6 6 5 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40 42 -- -- -- -- -- 18 5 65 50 15 5 5 30 5 35 5 65 50 15 -- -- 25 10 10 10 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 55 60 -- -- -- -- -- 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 14, 15, 16 13 13 13 13 13 13, 14, 15 13, 14, 15 13, 14, 15 13, 14, 15 13 13, 15 13 17 17 17 17 17 17 17 17 PORT B PERIPHERAL INTERFACE TIMING 2669 tbl 24 5.31 19 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V10%, T = 0C to +70C) A Commercial IDT72510L25 IDT72520L25 Symbol tbDSBH Parameter Min. 10 Max. -- PORT B RETRANSMIT and PARITY TIMING IDT72510L35 IDT72520L35 Min. 10 Max. -- IDT72510L50 IDT72520L50 Min. 15 Max. -- Unit ns Timing Figure 9, 18 RER, REW, LDRER, LDREW set-up and recovery time Parity error time tbPER 20 -- 25 -- 30 -- ns 19 BYPASS TIMING tBYA tBYD taBYDV Bypass access time Bypass delay Bypass data valid time from DSA -- -- 15 3 15 10 -- -- -- -- 15 3 20 15 -- -- -- -- 15 3 30 20 -- ns ns ns ns 16 16 16 16 tbBYDV (3) Bypass data valid time from DSB FLAG TIMING tREF tWEF tRFF tWFF tRAEF Read clock edge to Empty Flag asserted Write clock edge to Empty Flag not asserted Read clock edge to Full Flag not asserted Write clock edge to Full Flag asserted Read clock edge to Almost-Empty Flag asserted Write clock edge to Almost-Empty Flag not asserted Read clock edge to Almost-Full Flag not asserted Write clock edge to Almost-Full Flag asserted -- -- -- -- -- -- 25 25 25 25 40 -- -- -- -- -- 35 35 35 35 50 -- -- -- -- -- 45 45 45 45 60 ns ns ns ns ns 14, 15, 20, 22 14, 15, 20, 22 14, 15, 21, 23 14, 15, 21, 23 20, 22 tWAEF -- 40 -- 50 -- 60 ns 20, 22 tRAFF -- 40 -- 50 -- 60 ns 21, 23 tWAFF -- 40 -- 50 -- 60 ns 21, 23 2669 tbl 25 NOTES: 1. Read and Write are internal signals derived from DSA, R/WA , DSB, R/WB, RB, and WB. 2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are internal flags, the timing given is for those assigned to external pins. 3. Values guaranteed by design, not currently tested. 5.31 20 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE tRSC tRS RS tRSS (or R/WB, DSB ) tRSR WB, RB RER , REW LDRER LDREW REQ tRSR DSA tRSF FLGA, FLGC tRSF FLGB, FLGD Figure 9. Hardware Reset Timing for IDT72510/520 2669 drw 11 5.31 21 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE CSA A0, A1 R/WA DSA taS taH 2669 drw 12 Figure 10. Basic Port A Control Signal Timing (Applies to All Port A Timing) R/WA tWPW DSA tWRCOM Opcode DA8-DA12 or Operand DA0-DA2 2669 drw 13 taDS taDH Figure 11. Port A Command Timing (Write) 5.31 22 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE WRITE R/WA taWC taWPW DSA taS taWR taH Input DA0 - DA17 taDS taDH READ R/WA taRC taRPW DSA taS taRR taH Output DA0 - DA17 taLZ taA taDV taHZ 2669 drw 14 Figure 12. Read and Write Timing for Port A 5.31 23 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE WRITE tbWC (R/WB) (or DSB) WB tbWPW tbS tbWR tbH Input DB0-DB8 tbDS1 or tbDS2 tbDH1 or tbDH2 NOTES: 1. tbDS1 and tbDH1 are with parity checking or if parity is ignored, tbDS2 and tbDH2 are with parity generation. 2. RB = 1 (R/WB) (R/ B) tbRC (or DSB) tbS Output DB0-DB8 tbLZ tbA1 or tbA2 RB tbRPW READ tbRR tbH tbDV tbHZ 2669 drw 15 NOTES: 1. tbA1 is with parity checking or if parity is ignored, tbA2 is with parity generation. 2. RB = 1 Figure 13. Port B Read and Write Timing. Processor Interface Mode Only 5.31 24 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE AAEB FIFO WRITE FLOW-THROUGH taWPW DSA DA0-DA17 DATA INPUT taDS taDH AB Full Flag (1) tRFF RB (or DSB) tWFF tbLZ DB0-DB8 DATA OUT tbA1 or tbA2(2) tbDV DATA OUT tbHZ NOTES: 1. Assume the flag pin is programmed active LOW. 2. tbA1 is with parity checking or if parity is ignored, tbA2 is with parity generation. 3. R/WA = 0 BAEA FIFO READ FLOW-THROUGH taRPW DSA taLZ DA0-DA17 taA DATA OUTPUT taDV BA . Empty Flag (1) tWEF WB (or DSB) taHZ tREF DB0-DB8 DATA INPUT DATA INPUT tbDH1 or tbDH2(2) tbDS1 or tbDS2(2) NOTES: 1. Assume the flag pin is programmed active LOW. 2. tbDS1 & tbDH1 are with parity checking or if parity is ignored, tbDS2 & tbDH2 is with parity generation. 3. R/WA = 1 Figure 14. Port A Read and Write Flow-Through Timing. Processor Interface Mode Only 2669 drw 16 5.31 25 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE BAEA FIFO WRITE FLOW-THROUGH DSA taLZ DA0-DA17 taA BA (1) Full Flag tRFF tbWPW tWFF DATA OUT taHZ WB (or DSB) DB0-DB8 tbDS1 or tbDS2 (2) NOTES: 1. Assume the flag pin is programmed active LOW. 2. tbDS1 & tbDH1 are with parity checking or if parity is ignored, tbDS2 & tbDH2 are with parity generation. 3. R/WA = 1 DATA INPUT tbDH1 or tbDH12 (2) AAEB FIFO READ FLOW-THROUGH DSA DA0-DA17 taDS AB . Empty Flag (1) DATA INPUT taDH tWEF tbRPW tREF RB (or DSB) tbLZ DB0-DB8 tbA1 or tbA2 NOTES: 1. Assume the flag pin is programmed active LOW. 2. tbA1 is with parity checking or if parity is ignored, tbA2 is with parity generation. 3. R/WA = 0 DATA OUT tbDV DATA OUT tbHZ 2669 drw 17 Figure 15. Port B Read and Write Flow-Through Timing 5.31 26 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE BAEA READ BYPASS R/WA taS DSA taLZ DA0-DA7, DA16 BYTE 0 tBYA taDV (1) BYTE 1 taHZ BYTE 2 taH RB (2)(or DSB) tBYD tBYD (R/WB) tBYD (1) DB0-DB8 BYTE 0 BYTE 1 BYTE 2 tBYD tBYD NOTES: 1. Once the bypass starts, any data changes on Port B bus (Byte 0 AEByte 1) will be passed to Port A bus. 2. WB = 1. AAEB WRITE BYPASS R/WA taS taH DSA tBYD DA0-DA7, DA16 BYTE 0 tBYD (1) BYTE 1 BYTE 2 WB(2) (or DSB) tBYD (R/WB) tbLZ DB0-DB8 tBYA tBYD tbBYDV taBYDV BYTE 0 (1) tBYD BYTE 1 tbHZ BYTE 2 2669 drw 18 NOTES: 1. Once the bypass starts, any data changes on Port A bus (Byte 0 AEByte 1) will be passed to Port B bus. 2. RB = 1. Figure 16. Bypass Path Timing. BiFIFO Must be in Peripheral Interface Mode 5.31 27 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE SINGLE WORD DMA TRANSFER 2 to 5 cycles tCKC tCKH CLK REQ tREQS tREQH tCKL 1 cycle 1 to 2 cycles ACK WRITE (R/WB) tACKL tACKL WB (or DSB) tACKL Output DB0-DB17 tbLZ tbDV tbHZ READ (R/WB) tbA1 or tbA2 RB (or DSB) tACKL Input DB0-DB17 NOTES: 1. tbA1, tbDS1and tbDH1are with parity checking or if parity is ignored, tbA2 & tbDS2 and tbDH2 are with parity. tACKL tbDS1 or tbDS2 tbDH1 or tbDH2 2 to 5 cycles CLK REQ 1 to 2 cycles 2 to 5 cycles 1 to 2 cycles BLOCK DMA TRANSFER ACK, R/WB RB, WB (or DSB) 2669 drw 19 Figure 17. Port B Read and Write DMA Timing. Peripheral Interface Mode Only 5.31 28 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE (or R/WB, DSB) RB, WB RER, REW tbDSBH tbWPWH tbDSBH LDRER, LDREW 2669 drw 20 Figure 18. Port B Reread and Rewrite Timing for Intelligent Retransmit SET PARITY ERROR: FLGA IS ASSIGNED AS THE PARITY ERROR PIN R/WB tbS tbH RB, WB (or DSB) tPER FLGA CLEAR PARITY ERROR: COMMAND WRITTEN INTO PORT A CLEARS PARITY ERROR ON FLGA PIN R/WA taS taH DSA tPER FLGA NOTE: 1. FLGA is the only pin that can be assigned as a parity error output. Figure 19. Port B Parity Error Timing 2669 drw 21 5.31 29 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE DSA Write (or R/WB=0, 2n+1 2 3 4 tWEF 2n+2 Read 1 2 n+1 WB 1 DSB) tREF BA Empty Flag tWAEF BA AlmostEmpty Flag 2669 drw 22 tRAEF Figure 20. Empty and Almost-Empty Flag Timing for BAEA FIFO. (n = Programmed Offset) NOTES: 1. BAEA FIFO is initially empty. 2. Assume the flag pins are programmed active LOW. 3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads must be doubled. 4. R/WA = 1 Read DSA (or R/WB=0, 1 Write 1 2 3 tWAFF 4 2m+1 2m+2 2 m+1 WB DSB) tRAFF BA AlmostFull Flag tWFF BA Full Flag 2669 drw 23 tRFF Figure 21. Full and Almost-Full Flag Timing for BAEA FIFO. (m = Programmed Offset) NOTES: 1. BAEA FIFO initially contains D-(M+1) data words. D = 512 for IDT 72510; D = 1024 for IDT72520. 2. Assume the flag pins are programmed active LOW. 3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads must be doubled. 4. R/WA = 1 5.31 30 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE Write DSA RB (or R/WB=1, DS B) 1 2 n+1 Read 1 tWEF 2 3 4 tREF 2n+1 2n+2 AB Empty Flag tWAEF AB Almost-Empty Flag 2669 drw 24 tRAEF Figure 22. Empty and Almost-Empty Flag Timing for AAEB FIFO. (n = Programmed Offset) NOTES: 1. AAEB FIFO is initially empty. 2. Assume the flag pins are programmed active LOW. 3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads must be doubled. 4. R/WA = 1 Write DSA (or R/WB=1, DSB) 1 2 m+1 Read 1 2 3 4 tRAFF 2m+ 1 2m+ 2 RB BA Almost- Full Flag tWAFF tWFF BA Full Flag tRFF 2669 drw 25 Figure 23. Full and Almost-Full Flag Timing for AAEB FIFO. (m = Programmed Offset) NOTES: 1. AAEB FIFO initially contains D-(M+1) data words. D = 512 for IDT 72510; D = 1024 for IDT72520. 2. Assume the flag pins are programmed active LOW. 3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads must be doubled. 4. R/WA = 0 5.31 31 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type L Power XX Speed J Package Process/ Temperature Range Blank J 25 35 50 L 72510 72520 Commercial (0C to +70C) Plastic Leaded Chip Carrier Commerical Only Access Time (tA) in ns Low Power 512 x 18 -to- 1024 x 9 BiFIFO 1024 x 18 -to- 2048 x 9 BiFIFO 2669 drw 26 5.31 32 |
Price & Availability of IDT72510
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